IC Design Process: A Beginner's Overview to VLSI Technology

Description

This is a beginner level course.

When anybody start learning a hardware description language such as Systemverilog or VHDL, the most common problem they could face is, in ‘connecting’ what they write in their program to the actual ‘circuit’ that get produced in the Silicon. This is a course designed to simplify this problem by connecting together the pieces of information scattered throughout RTL design, functional verification, synthesis, physical design and manufacturing in VLSI technology.

This is not teaching any specific hardware description language, or anything related to coding in an HDL.

Who is the target audience?

• Beginner Systemverilog/ Verilog/ VHDL learners. This course is not for experts who know end to end process in the SoC design.